The long way round…
I’ve been playing around with FPGA’s, and using Xlinx Spartan 3 from Digilent, I mainly wanted it for the Sump Logic Analyser, but now branching out with it a bit, lets ignore the nightmare install that ISE Webpack is, then the fact that Digilent boards don’t work with the ISE programming tools and focus on the rest of the oddness..
First off VITAL, this is a library that ought to be in the IEEE lib’s, but for some reason ( possibly being a cut down version of the software, but if so wouldn’t it be nice if it said so ) . I managed to get this up and running by installing some software that had a VITAL2000 source code ( vhd’s) and adding them to my project as a new library, changed the USE and LIBRARY options to use VITAL2000 and VITAL_timing_2000 ( the lib i have appends _2000 to all of them ) , then its a case of marking some of the functions IMPURE, they’re just warnings so not really needed. XIinx’s website is no good, and their support forum didn’t turn up anything either.
I even switched to Altera Quartus at one point, but that had similar issues, seems they only have VITAL95 support, and I ran into other issues with it too.
After that the FMF library needs to be updated to use the new LIBRARY and USE settings… So i finally get to the point where the FMF library compiles, the VITAL2000 compiles, and off it goes to compile the model I’m using, brrp! nope, some mysterious error about ‘Port being unsupported in a Block concurrent statement’ over on the FMF site someone’s noted it from an old build and the admin is wondering if ISE WebPack is indeed a crippled version.
updated: uhh i guess you can’t use any of the FMF models for anything but simulation, or vital.. these are good things to learn early on its a core difference with software dev and fpga development!
As much used to cross development toolsets and so on, the FPGA has been the most difficult and painful route I’ve ever taken, and I’ve worked on some bizarre stuff, the programming itself is easy enough but the dev tools and support are horrible, I guess you just get spoiled by Microsoft’s level of devtool’s and support.
Anyway my ‘allotment’ for FPGA time is up for today, so I figured jot down a note that i can fill in later., and hoping that the FMF admin will have a solution..