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  • charliex 4:04 am on December 26, 2009 Permalink | Reply
    Tags: ISE, Xilinx   

    Xilinx ISE update 11.3 –> 11.4 

     

    So a new update appeared for ISE, and I installed it, took about two hours… Worked for about five minutes then failed with the usual Xilinx cryptic message system this one being,  ‘ error message, when i tried to edit the  .v I’d  just created and compiled earlier, refusing to edit the file.

    So i reverted the changes, another hour+ gone, just basically moving/deleting files!, quad core 3 GHz with a 10,000 RPM WD drive under XP. It uses lots and lots of little files, so disable any antivirus you have since it’ll kill the already terrible speed as well as ruin your disk space. Suggest Xilinx look into using a different system, single packed files perhaps ?., works for practically all the video games out there, WAD files etc.. 1000’s of small files is just bad, it always kills performance.

     

    Loading the project back into 11.3 i see it added a ‘timing message to the top of the file (first part of the error message above), so i removed it. Curious to see if that was the cause of the error, I’m reinstalling the patch (which is now downloading again)

     

    This is the uninstaller, fills you with hope doesn’t it! Started off ok, then after about 40% did this. My guess is memory corruption.

    xilinux_1

     

    I’m writing this as i wait for it to reinstall, 15% so far, started at 5:45PM  now 6:10PM, it is around a 2 Gb patch. 40% at 6:28PM (22 Mbps connection). Still at 40% at 6:38PM, and 40% at 6:46PM

     

      I wonder if they have they seen this XKCD comic ?

     

    Still at least I’ve got some episodes of Top Gear and Doctor Who to watch on TiVo. It is December 25th, I just can’t imagine there are many people downloading from xilinx.com and i did a few tests at speedtest.net etc, I’m getting plenty of bandwidth.

     

    Ok finally moved off 40% and now its in the make 100’s of backup folders to copy the existing files into for the rollback. Since the patch is so large it seems to replace just about everything. I’m wondering how long this would take instead ?

    1. recursive zip on all folders in ISE.
    2. delete/replace/add new files

    Or just rename the existing folder to backup_xxx and then install a fresh copy. Even a differential archive shouldn’t take this long. I’m watching it with Filemon from time to time, recursively generating deep directories and copying. We keep our software updates in a content management system like subversion, so you just update to the latest, and you can go back to older versions easily, releases are tagged.

     

    It’s fairly hammering along now thanks to the 10,000 RPM drive. 70% at 6:58PM, but I watched Jeremy Clarkson drive to the North Pole since this started. 79% and its stalled again , since its downloading more data. 83% 7:17 PM, 84%  7:33PM, and this is the second time today I’ve installed it, around 5 hours to install/rollback/reinstall and i don’t know if it’ll work. Woo Hoo 100% at 7:56PM , but whats this ?

    xilinx

     

    Yep 107% its just that awesome. Presumably now its decided to just change files that don’t belong to it, or updating some of my other software. So far its at 126% and its done, well after a reboot. 5:45PM started, 8:03PM finished ( well after the reboot )

     

    I’m curious to know how much of the data being downloaded is actually different.

     

    ISE is just an awful tool. We’re spoiled rotten with C/C++ tools like Developer Studio. FPGA’s are often used because they are fast, the coincidence isn’t lost on me. Best I can think of is, don’t use the updater, delete and redownload it in whole, or just leave it overnight.

     

    Seems to be ok now, I don’t know if I’ll get the original error or not.  ISE crashes very consistently after editing the timing constraints file.

     
  • charliex 6:45 pm on October 20, 2009 Permalink | Reply
    Tags: Altera, ISE, Spartan, WebPack   

    The long way round… 

    I’ve been playing around with FPGA’s, and using Xlinx Spartan 3 from Digilent, I mainly wanted it for the Sump Logic Analyser, but now branching out with it a bit, lets ignore the nightmare install that ISE Webpack is, then the fact that Digilent boards don’t work with the ISE programming tools and focus on the rest of the oddness..

    First off VITAL, this is a library that ought to be in the IEEE lib’s, but for some reason ( possibly being a cut down version of the software,  but if so wouldn’t it be nice if it said so ) . I managed to get this up and running by installing some software that had a VITAL2000 source code ( vhd’s) and adding them to my project as a new library, changed the USE and LIBRARY options to use VITAL2000 and VITAL_timing_2000 ( the lib i have appends _2000 to all of them ) , then its a case of marking some of the functions IMPURE, they’re just warnings so not really needed. XIinx’s website is no good, and their support forum didn’t turn up anything either.

    I even switched to Altera Quartus at one point, but that had similar issues, seems they only have VITAL95 support, and I ran into other issues with it too.

    After that the FMF library needs to be updated to use the new LIBRARY and USE settings… So i finally get to the point where the FMF library compiles, the VITAL2000 compiles, and off it goes to compile the model I’m using, brrp! nope, some mysterious error about ‘Port being unsupported in  a Block concurrent statement’  over on the FMF site someone’s noted it from an old build and the admin is wondering if ISE WebPack is indeed a crippled version.

    updated: uhh i guess you can’t use any of the FMF models for anything but simulation, or vital.. these are good things to learn early on its a core difference with software dev and fpga development!

    As much used to cross development toolsets and so on, the FPGA has been the most difficult and painful route I’ve ever taken, and I’ve worked on some bizarre stuff, the programming itself is easy enough but the dev tools and support are horrible, I guess you just get spoiled by Microsoft’s level of  devtool’s and support.

     

    Anyway my ‘allotment’ for FPGA time is up for today, so I figured jot down a note that i can fill in later., and hoping that the FMF admin will have a solution..

     
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